1. Field of the Inventive Concept
The present inventive concept relates to a semiconductor device including a metal silicide layer of uniform thickness and method for manufacturing the same.
2. Description of the Related Art
Integrated circuits formed on semiconductor materials implement microelectronic devices that are widely used in the design of digital logic circuits such as microprocessors and memory devices for products ranging from satellites to consumer electronics. Advances in semiconductor chip fabrication technology, including technology development and process improvement obtained through scaling for high speed and high integration density, have raised the performance of digital logic systems.
A semiconductor device including a formed silicide layer can be a field effect transistor (FET) which has a source region and a drain region. Field-effect transistors (FET) and other related insulated-gate electronic devices are main components of CMOS (complementary metal oxide circuits) integrated circuits. A MOSFET generally consists of two closely spaced, doped regions (the “source” and the “drain”) formed in a semiconductor substrate. The region between the two is the “channel.” A thin insulation layer is formed directly above the channel. A conductive material called the gate electrode is positioned directly over and completely covering the gate insulation layer directly above the channel. A voltage applied to the gate electrode affects the conductive properties of the channel region, whereby the FET is turned ON or OFF. A conductive material may be applied to the top surface of each of the “source” and the “drain” regions to provide electrical contacts (electrodes) which may be accessed through a contact hole. Manufacturers of integrated circuits typically form metal-silicide contacts, electrodes and interconnections between circuit components. See e.g., U.S. Pat. No. 4,337,476 (Fraser and Murarka).
According to a conventional method of forming a semiconductor device illustrated in U.S. Pat. No. 6,440,828 and US Patent Application 2005-0124128, an interlayer dielectric layer (ILD) is formed on the doped source and drain regions of the silicon layer, and then vertical openings are excavated through the interlayer dielectric layer to expose a portion of each source and drain region of silicon layer. Then the S/D regions exposed through the contact holes may then be amorphized by an ion implantation. Then a barrier metal layer is formed along the sidewalls of the contact hole and on the exposed S/D region. Then a silicide layer (55) is formed on the S/D region at the bottom of the contact hole by an additional heat-treatment. Then a conductive plug is formed in each vertical opening.
According to another conventional method of forming a semiconductor device, a silicide layer is formed on the S/D region firstly, and then, an interlayer dielectric layer is formed on the silicide layer, and then a vertical opening is excavated through the interlayer dielectric layer to expose the silicide layer, and then a conductive plug is formed in the vertical opening.
In order to form a low-resistivity contact with a semiconductor (substrate) in a contact hole, a refractory metal film is deposited so as to cover the contact area of the “source” and the “drain” regions of the semiconductor substrate. The next step is a heat-treatment during which the refractory metal reacts with the semiconductor material so as to produce a refractory metal silicide layer. Titanium is attractive, because the resulting titanium silicide (TiSi2) forms a low Schottky barrier with any one of the p-type semiconductors and the n-type semiconductors. Moreover, the titanium easily reduces natural oxide unavoidably covering the contact area.
The aspect ratio (height/width) of contact holes is getting larger and larger as the integration density increases. It is difficult, if not impossible, to properly deposit refractory metal on the bottom surface of a miniature contact hole having a large aspect ratio through a metal sputtering technique.
Semiconductor Device manufacturers attempt to use a chemical vapor deposition (CVD) so as to grow a refractory metal layer or a refractory metal silicide layer over the exposed semiconductor surface, especially in the miniature contact holes having the large aspect ratio. However, the refractory metal grows differently on the semiconductor surface depending upon the conductivity (dopant) type of the contact area. When the refractory metal is concurrently deposited on a heavily doped p-type contact area and a heavily doped n-type contact area, the refractory metal layer on the heavily doped p-type contact area can become different in thickness from the heavily doped n-type contact area. If one of the refractory metal layers is optimized, the other refractory metal layer is rendered thinner. On the other hand, if the other refractory metal layer is optimized, the refractory metal layer is too thick, and material is wasted and leakage current may be increased.
Currently, millions of FETs including silicide contacts are formed and interconnected in each semiconductor chip to construct microprocessors (CPUs), and nonvolatile memory circuits such as static random access memories (SRAM) and static random access memories (DRAM). Special FETs are used as memory cell transistors to store data in nonvolatile memory devices such as NAND flash memory devices and NOR flash memories. Each of the memory cell transistors stores 1-bit data or data of two or more bits. A nonvolatile memory cell FET capable of storing 1-bit data is called a single level cell (SLC). A nonvolatile memory cell FET capable of storing data of two or more bits is called a multi level cell (MLC).